View MB98C81233_717923.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds05-30338-2e fujitsu semiconductor data sheet flash memory card 5v-only flash miniature card mb98c81013(1mb)/81123(2mb)/81233(4mb)/81333(8mb)-10 1m/2m/4m/8m-byte 5 v-only flash miniature card the fujitsu flash miniature cards conform to ?iniature card speci?ation pubulished by mcif; miniature card implementers forum. the fujitsu flash miniature cards are small form factor flash memory cards targeted various markets; digital pho- tography, audio recording, hand held pcs and other small portable equipments. miniature cards high performance, small size (38 mm 33 mm 3.5 mm), low cost and simple interface are ideal for portable applications that require high speed ?sh disk drives or execute in place (xip). the flash miniature cards are 5 v-only operational and allow the users to use as 8 or 16 organization on low power at high speed. small size : 33.0 mm (length) 38.0 mm (width) 3.5 mm (thickness) +5 v 5% power supply program and erase command control for automated program/automated erase operation erase suspend read/program capability (only erase suspend read is possible for mb98c81013) 128 kb sector erase (at 16 mode) any combination of sectors erase and full chip erase detection of completion of program/erase operation with data# polling or toggle bit. ready/busy output with busy# (except for mb98c81013) reset function with reset# pin (except for mb98c81013) write protect function with wp switch low vcc write inhibit ais (attribute information structure) is available from the address ?000h of lower byte. this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
2 mb98c81013/81123/81233/81333-10 n package n descriptions differences mb98c81013 mb98c81123 MB98C81233 mb98c81333 density 1 mb 2 mb 4 mb 8 mb memory device 4 m bit 8 m bit 16 m bit ? quantity 2224 read 1 b unit ??? program 1 b unit ??? chip erase 512 kb unit 1 mb unit 2 mb unit ? sector erase 64 kb unit ??? number of sectors 16 32 64 128 erase suspend read yes yes yes yes erase suspend program no yes yes yes address a0 to a18 a0 to a19 a0 to a20 a0 to a21 reset# no yes yes yes busy# no yes yes yes write protect 8 m byte 5v operation flash memory (crd-60p-m01) 5 v - only flash miniature card
3 mb98c81013/81123/81233/81333-10 memory map chip3,2 chip1,0 chip1,0 chip1,0 mb98c81013 4m bit 2 mb98c81123 8m bit 2 MB98C81233 16m bit 2 mb98c81333 16m bit 4 4 mw 2 mw 1 mw 512 kw chip1,0
4 mb98c81013/81123/81233/81333-10 n pad assignments * : a 19 , a 20 , a 21 are ?.c. for each product. see ?escriptions? pad no symbol pad no symbol pad no symbol pad no symbol 1a 18 16 n.c. 31 a 19 * 46 cd# 2a 16 17 n.c. 32 a 17 47 a 21 * 3a 14 18 oe# 33 a 15 48 busy# 4 n.c. 19 d 15 34 a 13 49 we# 5 ceh# 20 d 13 35 a 12 50 d 14 6a 11 21 d 12 36 reset# 51 rfu 7a 9 22 d 10 37 a 10 52 d 11 8a 8 23 d 9 38 vs1# 53 vs2# 9a 6 24 d 0 39 a 7 54 d 8 10 a 5 25 d 2 40 n.c. 55 d 1 11 a 3 26 d 4 41 a 4 56 d 3 12 a 2 27 n.c. 42 cel# 57 d 5 13 a 0 28 d 7 43 a 1 58 d 6 14 n.c. 29 n.c. 44 n.c. 59 n.c. 15 n.c. 30 n.c. 45 n.c. 60 a 20 * ex 1 v cc ex 2 gnd ex 3 cins#
5 mb98c81013/81123/81233/81333-10 n pad descriptions * : take notice that those pads are connected internally. n pad locations symbol i/o pad name symbol i/o pad name a 0 to a 21 i address input busy# o ready/busy d 0 to d 15 i/o data input/output cd# o card detect * cel# i card enable for lower byte vs1#, vs2# o voltage sense ceh# i card enable for upper byte n.c. non connection oe# i output enable v cc power supply we# i write enable gnd ground reset# i hardware reset cins# o card insertion * 60 30 31 1 ex 1 ex 3 ex 2 fig. 1 ? bottom view v cc key v cc key: see ?nique features?
6 mb98c81013/81123/81233/81333-10 n block diagram mb98c81013, mb98c81123 and MB98C81233 fig. 2.1 ? block diagram gnd internal circuit internal circuit vcc 100k vcc n.c. address i/o r/b even flash memory 4m bit 1 (mb98c81013) 8m bit 1 (mb98c81123) 16m bit 1 (MB98C81233) address i/o r/b reset we oe ce address odd flash memory 4m bit 1 (mb98c81013) 8m bit 1 (mb98c81123) 16m bit 1 (MB98C81233) reset# * cins# cd# busy# * 10k vcc 100k vcc 100k cel# ceh# oe# d0 to d7 d8 to d15 vcc n.c. vs1# vs2# we# write protect switch reset we oe ce n.c. * : except for mb98c81013.
7 mb98c81013/81123/81233/81333-10 mb98c81333 fig. 2.2 ? block diagram gnd internal circuit internal circuit vcc 100k vcc n.c. address i/o r/b reset we oe ce even flash memory 16m bit 2 (mb98c81333) address i/o r/b reset we oe ce address reset# cins# cd# busy# 10k vcc 100k vcc 100k cel# ceh# oe# d0 to d7 d8 to d15 vcc n.c. vs1# vs2# we# write protect switch odd flash memory 16m bit 2 (mb98c81333) a /g1 /g2 1y 2y a21 2 2 decoder n.c.
8 mb98c81013/81123/81233/81333-10 n chip and sector decoding erase sector decoding table notes: *1. a 19 is not availabe for mb98c81013. mb98c81013 has 8 sectors. *2. a 20 is not availabe for mb98c81013 and mb98c81123. mb98c81013 has 8 sectors and mb98c81123 has 16 sectors. sector address (sa) a 20 * 2 a 19 * 1 a 18 a 17 a 16 sector 31 11111 sector 30 11110 sector 29 11101 total 32 sectors * 1 * 2 per 1 chip sector 2 0 0 0 1 0 sector 1 0 0 0 0 1 sector 0 0 0 0 0 0
9 mb98c81013/81123/81233/81333-10 n chip configuration the miniature cards use 2 or 4 pcs of flash memory. 2 pcs of flash memory are operated simultaneously at 16 bit mode and even number of chip is applied to lower byte and odd number of chip is applied to upper byte. at 8 bit mode, even address and odd address are selected with cel# and ceh#. 16 bit mode 1 cel# = ?? ceh# = ? : : odd number of chip + even number of chip odd number of chip + even number of chip odd number of chip + even number of chip odd number of chip + even number of chip d15 d0 003h 002h 001h 000h 2 8 bit mode cel# = ?? ceh# = ? : : odd number of chip odd number of chip odd number of chip odd number of chip d15 d8 003h 002h 001h 000h cel# = ?? ceh# = ? : : even number of chip even number of chip even number of chip even number of chip d7 d0 003h 002h 001h 000h
10 mb98c81013/81123/81233/81333-10 n function descriptions 1. read mode the data in the common can be read with ?e# = vil and ?e# = vih? the address is selected with a0-a21. and cel# and ceh# select output mode. 2. standby mode cel# and ceh# at ?ih place the card in standby mode. d0-d15 are placed in a high-z state independent of the status ?e# and ?e#? 3. output disable mode the outputs are disabled with oe# and we# at ?ih? d0-d15 are placed in high-z state. 4. write mode the card is in write mode with ?e# = vih and ?e# and ce# = vil? commands can be written at the write mode. two types of the write mode, ?e# control and ?e# control are available. 5. command de?itions user can select the card operation by writing the speci? address and data sequences into the command register. if incollect address and data are written or improper sequence is done, the card is reseted to read mode. see ?ommand definision table? 6. automated program capability programming operation can switch the data from ? to ?? the data is programmed on a byte-by-byte or word-by-word basis. the card will automatically provide adequate internally generated programming pulses and verify the pro- grammed cell margin by writing four bus cycle operation. the card returns to common memory read mode automatically after the programming is completed. addresses are latched at falling edge of we# or ce# and data is latched at rising edge of we# or ce#. the fourth rising edge of we# or ce# on the command write cycle begins programming operation. we can check whether a byte (word) programming operation is completed successfully by sequence ?g with busy# (except mb98c81013), data# polling or toggle bit function. see ?rite operation status? any commands written to the chip during programming operation will be ignored. 7. automated chip erase capability we can execute chip erase operation by 6 bus cycle operation. chip erase does not require the user to program the chip prior to erase. upon executing the erase command sequence the chip automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timing during these operations. the card returns to common memory read mode automatically after the chip erasing is completed. whether or not chip erase operation is completed successfully can be checked by sequence ?g with busy# (except mb98c81013), data# polling or toggle bit function. see ?rite operation status? any commands written to the chip during programming operation will be ignored.
11 mb98c81013/81123/81233/81333-10 8. automated sector erase capability we can execute the erase operation on any sectors by 6 bus cycle operation. a time-out of 50 m s (typ.) from the rising edge of the last sector erase command will initiate the sector erase command(s). multiple sectors in a chip can be erased concurrently. this sequence is followed with writes of 30h to addresses in other sectors desired to be concurrently erased. the time between writes 30h must be less than 50 m s, otherwise that command will not be accepted. any command other than sector erase or erase suspend during this time-out period will reset the chip to read mode. the automated sector erase begins after the 50 m s (typ.) time out from the rising edge of we# pulse for the last sector erase command pulse. whether the sector erase window is still open can be monitored with d3 and d11. sector erase does not require the user to program the chip prior to erase. the chip automatically programs ? to all memory locations in the sector(s) prior to electrical erase. the system is not required to provide any controls or timing during these operations. the card returns to common memory read mode automatically after the chip erasing is completed. whether or not sector erase operation is completed successfully can be checked by sequence ?g with busy#, data# polling or toggle bit function. the sequence ?g must be read from the address of the sector involved in erase operation. see ?rite operation status? 9. erase suspend erase suspend command allows the user to interrupt the sector erase operation and then do data reads or program from or to a non-busy sector in the chip which has the sector(s) suspended erase (only data read is possible for mb98c81013). this command is applicable only during the sector erase operation (including the sector erase time-out period after the sector erase commands 30h) and will be ignored if written during the chip erase or programming operation. writing this command during the time-out will result in immediate termination of the time-out period. the addresses are ?on? cares in wrinting the erase suspend or resume commands in the chip. when the erase suspend command is written during a sector erase operation, the chip will enter the erase suspend read mode. user can read the data from other sectors than those in suspention. the read operation from sectors in suspention results d 2 /d 10 toggling except mb98c81013. user can program to non-busy sectors by writing program commands except mb98c81013. a read from a sector being erase suspended may result in invalid data. 10. intelligent identi?r (id) read mode each common memory can execute an intelligent identi?r operation, initiated by writing intelligent id com- mand (90h). following the command write, a read cycle from address 00h retrieves the manufacture code, and a read cycle from address 01h returns the device code as follows. to terminate the operation, it is necessary to write read/reset command. 11. hardware reset (not applied for mb98c81013) the card may be reset by driving the reset# pin to vil. the reset# pin must be kept high (vil) for at least 500 ns. any operation in progress will be terminated and the card will be reset to the read mode 20 m s after the reset# pin is driven low. if a hardware reset occurs during a program operation, the data at that particular location will be indeterminate. when the reset# pin is low and the internal reset is complete, the card goes to standby mode and cannot be accessed. also, note that all the data output pins are high-z for the duration of the reset# pulse. once the reset# pin is taken high, the card requires 500 ns of wake up time until outputs are valid for read access. if hardware reset occurs during a erase operation, there is a possibility that the erasing sector(s) cannot be used.
12 mb98c81013/81123/81233/81333-10 12. data protection the card has wp (write protect) switch for write lockout. to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than 3.2 v. if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above 3.2 v. if v cc would be less than v lko during program/erase operation, the operation will stop. and after that, the operation will not resume even if v cc returns recommended voltage level. therefore, program command must be written again because the data on the address interrupted program operation is invalid. and regarding interrupting erase operation, there is possibility that the erasing sector(s) cannot be used. noise pulses of less than 5 ns (typical) on oe#, ce# or we# will not initiate a write cycle.
13 mb98c81013/81123/81233/81333-10 n function truth table h : ? level, l : ? level , x : ? or ? notes: *1. wpsw = write protect switch, np = non-protect, p = protect *2. except for mb98c81013. mode reset# * 2 ceh# cel# oe# we# wpsw * 1 data input/output d8 to d15 d0 to d7 hardware reset l x x x x p or np high-z high-z standby h h h x x p or np high-z high-z read ( 8 bit) hl l h p or np high-z dout l h dout high-z read ( 16 bit) l l dout dout write ( 8 bit) hl hl np high-z din l h din high-z write ( 16 bit) l l din din output disable hl p high-z high-z l h high-z high-z l l high-z high-z
14 mb98c81013/81123/81233/81333-10 n command definition table command table for 8-bit mode note: ca: chip address. (address in chip selected by a21 for mb98c81333) sa: sector address (address in 64 kb selected by a16, a17, a18, a19, a20 and a21) pa: program address (address to be programmed) ra: read address (address to be read) ia: intelligent id read address (manufacture code 0000h, device code 0001h) pd: programming data rd: read data id: intelligent identi?r (id) code command bus cycle 1st bus write cycle 2nd bus write/read cycle 3rd bus write cycle 4th bus write/read cycle 5th bus write cycle 6th bus write cycle read/reset 1 2 write read ca f0h ra rd read/reset 2 4 write write write read rcma1 aah rcma2 55h rcma1 f0h ra rd read intelligent id codes 4 write write write read icma1 aah icma2 55h icma1 90h ia id byte program 4 write write write write pcma1 aah pcma2 55h pcma1 a0h pa pd sector erase 6 write write write write write write scma1 aah scma2 55h scma1 80h scma1 aah scma2 55h sa 30h chip erase 6 write write write write write write ccma1 aah ccma2 55h ccma1 80h ccma1 aah ccma2 55h ccma1 10h sector erase suspend 1 write ca b0h sector erase resume 1 write ca 30h ccma1, ccma2: command address for chip erase scma1, scma2: command address for sector erase pcma1, pcma2: command address for program rcma1, rcma2: command address for read/reset icma1, icma2: command address for intelligent id read see ?ommand address table for 8-bit mode in page 16.
15 mb98c81013/81123/81233/81333-10 command table for 16-bit mode note: ca: chip address. (address in chip selected by a21 for mb98c81333) sa: sector address (address in 128 kb selected by a16, a17, a18, a19, a20 and a21) pa: program address (address to be programmed) ra: read address (address to be read) ia: intelligent id read address (manufacture code 0000h, device code 0001h) pd: programming data rd: read data id: intelligent identi?r (id) code command bus cycle 1st bus write cycle 2nd bus write/read cycle 3rd bus write cycle 4th bus write/read cycle 5th bus write cycle 6th bus write cycle read/reset 1 2 write read ca f0f0h ra rd read/reset 2 4 write write write read rcma1 aaaah rcma2 5555h rcma1 f0f0h ra rd read intelligent id codes 4 write write write read icma1 aaaah icma2 5555h icma1 9090h ia id byte program 4 write write write write pcma1 aaaah pcma2 5555h pcma1 a0a0h pa pd sector erase 6 write write write write write write scma1 aaaah scma2 5555h scma1 8080h scma1 aaaah scma2 5555h sa 3030h chip erase 6 write write write write write write ccma1 aaaah ccma2 5555h ccma1 8080h ccma1 aaaah ccma2 5555h ccma1 1010h sector erase suspend 1 write ca b0b0h sector erase resume 1 write ca 3030h ccma1, ccma2: command address for chip erase scma1, scma2: command address for sector erase pcma1, pcma2: command address for program rcma1, rcma2: command address for read/reset icma1, icma2: command address for intelligent id read see ?ommand address table for 16-bit mode in page 16.
16 mb98c81013/81123/81233/81333-10 command address table for 8-bit and 16-bit mode command address mb98c81013 mb98c81123 MB98C81233, mb98c81333 ccma1 5555h 555h ca ccma2 2aaah 2aah ca scma1 5555h 555h ca scma2 2aaah 2aah ca pcma1 5555h 555h ca pcma2 2aaah 2aah ca rcma1 5555h 555h ca rcma2 2aaah 2aah ca icma1 5555h 555h ca icma2 2aaah 2aah ca
17 mb98c81013/81123/81233/81333-10 n write operation status hardware sequence flag table (1): erase suspended sector (2): non-erase suspended sector notes: *1. performing successive read operations from the erase-suspended sector will cause d 2 , d 10 to toggle. *2. performing successive read operations from any address will cause d 6 , d 14 to toggle. *3. reading the byte address being programmed while in the erase-suspend program mode will indicate logic ? at the d 2 , d 10 bit. however, successive reads from the erase-suspended sector will cause d 2 , d 10 to toggle. *4. not applied for mb98c81013. d7, d15 (data# polling) the card features data# polling as a method to indicate to the host that the program/erase operation are in progress or completed. during the program operation an attempt to read the program address will produce the compliment of the data last written to d 7 /d 15 . upon completion of the program operation, an attempt to read the program address will produce the true data last written to d 7 /d 15 . during the erase operation, an attempt to read the program address will produce a ? at the d 7 /d 15 output. upon completion of the erase operation an attempt to read the device will produce a ? at the d 7 /d 15 output. for chip erase, the data# polling is valid after the rising edge of the sixth we# pulse in the six write pulse sequence. for sector erase, the data# polling is valid after the last rising edge of the sector erase we# pulse. even if the device has completed the operation and d 7 /d 15 has a valid data, the data outputs on d 0 to d 6 /d 8 to d 14 may be still invalid. the valid data on d 0 to d 7 /d 8 to d 15 will be read on the successive read attempts. the data# polling feature is only active during the programming operation, erase operation, sector erase time- out, erase suspend read mode and erase supend program mode. d6, d14 (toggle bit i) the card also features the ?oggle bit as a method to indicate to the host system that the program/erase operation are in progress or completed. during an program or erase cycle, successive attempts to read (oe# or ce# toggling) data from the card will result in d 6 /d 14 toggling between one and zero. once the program or erase cycle is completed, d 6 /d 14 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit is valid after the rising edge of the fourth we# pulse in the four write pulse sequence. for chip erase, the toggle bit is valid after the rising edge of the sixth we# pulse in the six write pulse sequence. for sector erase, the toggle bit is valid after the last rising edge of the sector erase we# pulse. the toggle bit is also active during the sector time out. either ce# or oe# toggling will cause the d 6 /d 14 to toggle. status d 7 , d 15 d 6 , d 14 d 5 , d 13 d 3 , d 11 d 2 , d 10 * 4 r/b# * 4 in progress programming d 7 #, d 15 # toggle 0010 erasing 0 toggle 0 1 toggle 0 erase suspend read (1)1100 toggle * 1 1 (2) data data data data data 1 erase suspend * 4 program d 7 #, d 15 # toggle * 2 00 * 1, * 3 0 exceeded time limits programming d 7 #, d 15 # toggle 1010 erasing 0 toggle 1 1 n/a 0 erase suspend * 4 program d 7 #, d 15 # toggle 1 0 n/a 0
18 mb98c81013/81123/81233/81333-10 d5, d13 (exceeded timing limits) d 5 /d 13 will indicate if the program or erase time has exceeded the speci?d limits (internal pulse count). under these conditions d 5 /d 13 will produce a ?? this is a failure condition which indicates that the program or erase cycle was not successfully completed. data# polling is the only operating function of the card under this condition. if this failure condition occurs during sector erase operation, it speci?s that a particular sector is bad and it may not be reused, however, other sectors are still functional and may be used for the program or erase operation. the chip must be reset to use other sectors. write the reset command sequence to the chip, and then execute program or erase command sequence. this allows the system to continue to use the other active sectors in the chip. if this failure condition occurs during the chip erase operation, it speci?s that the entire chip is bad or combination of sectors are bad. if this failure condition occurs during the byte programming operation, it speci?s that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused). the d 5 /d 13 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the card locks out and never completes the card operation. hence, the system never reads a valid data on d 7 /d 15 bit and d 6 /d 14 never stops toggling. once the card has exceeded timing limits, the d 5 /d 13 bit will indicate a ?? please note that this is not a device failure condition since the device was incorrectly used. d3, d11 (sector erase timer) after the completion of the initial sector erase command sequence the sector erase time-out will begin. d 3 /d 11 will remain low until the time-out is complete. data# polling and toggle bit are valid after the initial sector erase command sequence. if data# polling or the toggle bit indicates the card has been written with a valid erase command, d 3 /d 11 may be used to determine if the sector erase timer window is still open. if d 3 /d 11 is high (?? the internally controlled erase cycle has begun; attempts to write subsequent commands to the card will be ignored until the erase operation is completed as indicated by data# polling or toggle bit. if d 3 /d 11 is low (??, the card will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of d 3 /d 11 prior to and following each subsequent sector erase command. if d 3 /d 11 were high on the second status check, the command may not have been accepted. refer to table: hardware sequence flags. d2, d10 (toggle bit ii, not applied for mb98c81013) this toggle bit, along with d 6 , can be used to determine whether the card is in the erase operation or in erase suspend. successive reads from the erasing sector will cause d 2 to toggle during the erase operation. if the card is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause d 2 to toggle. when the card is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic ? at the d 2 bit. d 6 is different from d 2 in that d 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. busy# (ready/busy, not applied for mb98c81013) the card provides a busy# open-drain output pin as a way to indicate to the system that the program or erase operation are either in progress or has been completed. if the output is low, the card is busy with either a program or erase operation. if the card is placed in an erase suspend mode, the busy# output will be high. during programming, the busy# pin is driven low after the rising edge of the fourth we# pulse. during an erase operation, the busy# pin is driven low after the rising edge of the sixth we# pulse. the busy# pin will indicate a busy condition during the reset# pulse.
19 mb98c81013/81123/81233/81333-10 n program/erase flowchart fig. 3 ? program flowchart start set pa yes completed data# polling, toggle bit or busy# * 1 (see fig. 7, 8, 9, 10) set address pcma1, pcma2 * 2 write command (pcma1/aah or aaaah) * 2 write command (pcma2/55h or 5555h) * 2 write command (pcma1/a0h/a0a0h) * 2 write data (pa/pd) last address ? increment pa no pd : program data pa : program address *1. except mb98c81013 *2. see ?ommand definition table?
20 mb98c81013/81123/81233/81333-10 fig. 4 ? chip erase flowchart start set ca no completed write command (ccma1/aah or aaaah) * 2 write command (ccma2/55h or 5555h) * 2 write command (ccma1/80h or 8080h) * 2 desired other chips erase ? increment ca yes ca : chip address *1. except mb98c81013 *2. see ?ommand definition table? write command (ccma1/aah or aaaah) * 2 write command (ccma2/55h or 5555h) * 2 write command (ccma1/10h or 1010h) * 2 set address (ccma1, ccma2) * 2 data# polling, toggle bit or busy# * 1 (see fig. 7, 8, 9, 10)
21 mb98c81013/81123/81233/81333-10 fig. 5 ? sector erase flowchart set sa no completed write command (scma1/aah or aaaah) * 3 write command (scma2/55h or 5555h) * 3 desired other sectors erase ? * 2 yes sa : sector address *1. except mb98c81013 *2. possible for the sectors in a chip *3. see ?ommand definition table? set address scma1, scma2 * 3 write command (sa/30h or 3030h) start write command (scma1/80h or 8080h) * 3 write command (scma1/aah or aaaah) * 3 write command (scma2/55h or 5555h) * 3 write command (sa/30h or 3030h) data# polling, toggle bit or busy# * 1 (see fig. 7, 8, 9, 10)
22 mb98c81013/81123/81233/81333-10 fig. 6 ? erase suspend flowchart no finished ye s ca : chip address sa : sector address ra : read address *1. detection whether suspend mode is valid can be done by data# polling and busy# also. (mb98c81013 does not have busy#). *2. only read operation for mb98c81013. executing sector erase read data (sa) * 1 toggle bit = toggle? * 1 read or program * 2 stop erase suspend mode? write command (ca/30h or 3030h) no ye s write command (ca/b0h or b0b0h)
23 mb98c81013/81123/81233/81333-10 fig. 7 ? data# polling flowchart: x8 bit mode timer start * 1 no ye s *1. user sets the time period referring to ?rogram and erase performances? *2. program va = pa chip erase va = ca sector erase va = sa *3. d 5 /d 7 are for even chip(s). in the case of odd chip(s), d 5 ? d 13 and d 7 ? d 15 are applied. start read (va) * 2 d 7 = data? * 3 no ye s d 5 = 1 or time-up? * 3 read (va) * 2 d 7 = data? * 3 error completed ye s no
24 mb98c81013/81123/81233/81333-10 fig. 8 ? toggle bit flowchart: x8 bit mode timer start * 1 ye s no *1. user sets the time period referring to ?rogram and erase performances? *2. program va = pa chip erase va = ca sector erase va = sa *3. d 5 /d 6 are for even chip(s). in the case of odd chip(s), d 5 ? d 13 and d 6 ? d 14 are applied. start read (va) * 2 d 6 = toggle? * 3 no ye s d 5 = 1 or time-up? * 3 read (va) * 2 d 6 = toggle? * 3 error completed no ye s
25 mb98c81013/81123/81233/81333-10 fig. 9 ? data# polling flowchart: x16 bit mode timer start * 1 no ye s *1. user sets the time period referring to ?rogram and erase performances? *2. program va = pa chip erase va = ca sector erase va = sa ef: error flag ef = 0: operation completed ef = 1: lower byte error ef = 2: upper byte error ef = 3: lower/upper byte error start read (va) * 2 no ye s d 5 = 1 or time-up? read (va) * 2 ef = 1 ye s no d 7 = data? d 7 = data? 1 no ye s read (va) * 1 no ye s d 13 = 1 or time-up? read (va) * 2 ef = ef+2 ye s no d 15 = data? d 15 = data? 1 ye s ef = 0? error completed no ef = 0
26 mb98c81013/81123/81233/81333-10 timer start * 1 ye s no *1. user sets the time period referring to ?rogram and erase performances? *2. program va = pa chip erase va = ca sector erase va = sa ef: error flag ef = 0: operation completed ef = 1: lower byte error ef = 2: upper byte error ef = 3: lower/upper byte error start read (va) * 2 no ye s d 5 = 1 or time-up? read (va) * 2 ef = 1 no ye s d 6 = toggle? d 6 = toggle? 1 ye s no read (va) * 1 no ye s d 13 = 1 or time-up? read (va) * 2 ef = ef+2 no ye s d 14 = toggle? d 14 = toggle? 1 ye s ef = 0? error completed no ef = 0 fig. 10 ? toggle bit flowchart: x16 bit mode
27 mb98c81013/81123/81233/81333-10 n absolute maximum ratings *1 *1. permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n recommended operating conditions n dc characteristics notes: *1. this value does not apply to cel#, ceh# and we#. *2. this value does not apply to cd# and cins#. *3. for mb98c81013. parameter symbol value unit supply voltage v cc ?.5 to +6.0 v input voltage v in ?.5 to v cc +0.5 v output voltage v out ?.5 to v cc +0.5 v temperature under bias t a 0 to +60 c storage temperature t stg ?0 to +70 c parameter symbol min typ max unit v cc supply voltage v cc 4.75 5.0 5.25 v ground gnd 0 v ambient temperature t a 055 c parameter test conditions symbol value unit min typ max input leakage current * 1 v cc = v cc max., v in = gnd or v cc i li 10 m a output leakage current * 2 v cc = v cc max., v in = gnd or v cc i lo 10 m a standby current v cc = v cc max., cel#, ceh# = v cc v in = gnd or v cc i sb1 20 100 (250 * 3 ) m a cel#, ceh#, reset# = v ih i sb2 5.0 ma active read current cel#, ceh# = v il , cycle = 150 ns oe# = v ih i cc1 70 100 ma program current program in progress ( 16 mode) i cc2 80 150 ma erase current erase in progress ( 16 mode) i cc3 80 150 ma input low voltage v il ?.5 0.8 v input high voltage v ih 0.7 v cc ? cc +0.5 v output low voltage i ol = 12 ma, v cc = v cc min. v ol 0.45 v output high voltage i oh = ?.5 ma, v cc = v cc min. v oh 2.4 v low v cc lock-out voltage ? lko 3.2 3.7 4.2 v
28 mb98c81013/81123/81233/81333-10 n capacitance (t a = 25 c, f = 1 mhz, v in = v i/o = gnd) notes: *1. this value does not apply to cel#, ceh# and we#. *2. this value does not apply to cd# and cins#. n ac test conditions input pulse levels: v ih = 4.2 v, v il = 0.45 v input pulse rise and fall times: 5 ns timing reference levels input: v il = 0.8 v, v ih = 3.8 v output: v ol = 0.8 v, v oh = 2.0 v output load: 1ttl +100 pf n program and erase performances (mb98c81013) notes: *1. excludes system-level overhead. *2. excludes 00h programming prior to erasure. (mb98c81123) notes: *1. excludes system-level overhead. *2. excludes 00h programming prior to erasure. parameter symbol min max unit input capacitance * 1 c in 40 pf i/o capacitance * 2 c i/o 40 pf parameter min typ max unit byte program time * 1 8 500 m s chip programming time * 1 4.2 25 sec. sector erase time * 2 1 15 sec. program/erase cycles 100,000 cycles parameter min typ max unit byte program time * 1 8 2000 m s chip programming time * 1 8.4 50 sec. sector erase time * 2 1 15 sec. program/erase cycles 100,000 cycles
29 mb98c81013/81123/81233/81333-10 (MB98C81233, 81333) notes: *1. excludes system-level overhead. *2. excludes 00h programming prior to erasure. n ac characteristics (recommended operating conditions unless otherwise noted.) read cycle * 1 notes: *1. rise/fall time < 5 ns. *2. transition is measured at the point of 500 mv from steady state voltage. parameter min typ max unit byte program time * 1 8 500 m s chip programming time * 1 16.8 100 sec. sector erase time * 2 1 15 sec. program/erase cycles 100,000 1,000,000 cycles parameter symbol min max unit read cycle time t rc 100 ns card enable access time t ce 100 ns address access time t acc 100 ns output enable access time t oe 50 ns card enable to output in low-z * 2 t clz 5ns card disable to output in high-z * 2 t chz 50 ns output enable to output in low-z * 2 t olz 5ns output disable to output in high-z * 2 t ohz 50 ns output hold from address change t oh 0ns ready time from reset# t rdy 20 m s
30 mb98c81013/81123/81233/81333-10 program/erase cycle notes: *1. these do not include the preprogramming time. *2. not 100% tested. parameter symbol min typ max unit write cycle time t wc 100 ns address setup time t as 10 ns address hold time t ah 10 ns data setup time t ds 40 ns data hold time t dh 15 ns read recovery time (we# control) t ghwl 10 ns read recovery time (ce# control) t ghel 10 ns output enable hold time t oeh 20 ns card enable setup time t cs 20 ns card enable hold time t ch 10 ns write enable pulse width t wp 60 ns write enable setup time t ws 0ns write enable hold time t wh 10 ns card enable pulse width t cp 80 ns duration of byte program operation (/we control) t whwh1 8 m s duration of erase operation * 1 (/we control) t whwh2 115s duration of byte program operation (/ce control) t eheh1 8 m s duration of erase operation * 1 (/ce control) t eheh2 115s v cc setup time * 2 t vcs 50 m s reset pulse width t rp 500 ns busy delay time t bsy 40 ns
31 mb98c81013/81123/81233/81333-10 n timing diagram read cycle timing diagram (we# = v ih , reset# = v ih ) read cycle ( 8 bit mode): ?el# = oe# = v il , ceh# = v ih or ?eh# = oe# = v il , cel# = v ih addresses d0-d7 or d8-d15 previous data valid data valid t acc t oh v ih v il v oh v ol previous data valid data valid read cycle ( 16 bit mode): cel# = ceh# = oe# = v il d0-d15 v ih v il v oh v ol :unde?ed t rc t rc t acc t oh addresses
32 mb98c81013/81123/81233/81333-10 read cycle timing diagram (continued) (we# = v ih , reset# = v ih ) :unde?ed oe# ce1# or ce2# read cycle 3: 8-bit bus organization addresses high-z data valid t acc v ih v il v oh v ol t ce v ih v il v ih v il t clz t olz t chz t ohz d0-d7 or d8-d15 t oe
33 mb98c81013/81123/81233/81333-10 read cycle timing diagram (continued) (we# = v ih , reset# = v ih ) :unde?ed read cycle 4: cel# = ceh# = v il : 16-bit bus organization d0-d15 addresses v ih v il v oh v ol v ih v il v ih v il high-z data valid t ce t clz t olz t chz t ohz oe# cel#=ceh# t acc t oe
34 mb98c81013/81123/81233/81333-10 program cycle timing diagram (we# = controlled, reset# = v ih ) notes: *1. see ?unction truth table? *2. pcma1/pcma2 = command address for program, pa = program address, pd = program data. see ?ommand definition table? :unde?ed addresses * 1 v ih v il v ih v il v ih v il v ih v il data * 1 v ih/oh v il/ol v cc t wc t rc t as t ah t rc pcma1 * 2 pcma2 * 2 pcma1 * 2 pa * 2 pa * 2 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle data# polling cycle aah (aaaah) 55h (5555h) a0h (a0a0h) pd * 2 d7#, d15# pd * 2 data t oeh t whwh1 t wph t cs t ch t ghwl t wp t ds t vcs t dh oe# we# t bsy v oh v ol reset# ce# * 1
35 mb98c81013/81123/81233/81333-10 program cycle timing diagram (ce# = controlled, reset# = v ih ) notes: *1. see ?unction truth table? *2. pcma1/pcma2 = command address for program, pa = program address, pd = program data. see ?ommand definition table? :unde?ed addresses * 1 v ih v il v ih v il v ih v il v ih v il data * 1 v ih/oh v il/ol v cc t wc t rc t as t ah t rc pcma1 * 2 pcma2 * 2 pcma1 * 2 pa * 2 pa * 2 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle data# polling cycle aah (aaaah) 55h (5555h) a0h (a0a0h) pd * 2 d7#, d15# pd * 2 data t oeh t eheh1 t cph t ws t wh t ghel t cp t ds t vcs t dh oe# we# ce# * 1 t bsy busy# v oh v ol
36 mb98c81013/81123/81233/81333-10 erase cycle timing diagram (we# = controlled, reset# = v ih ) notes: *1. see ?unction truth table? *2. ccma1/ccma2 = command address for chip erase, scma1/scma2 = command address for sector erase, sa = sector address. see ?ommand definition table? :unde?ed addresses * 1 v ih v il v ih v il v ih v il v ih v il data * 1 v ih/oh v il/ol v cc t wc t as t ah ccma1/ scma1 * 2 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle aah (aaaah) 55h (5555h) 80h (8080h) t wph t cs t ch t ghwl t wp t ds t vcs t dh aah (aaaah) 55h (5555h) 10h/30h (1010h/3030h) 5th bus cycle 6th bus cycle ccma1/ sa * 2 oe# we# ce# * 1 ccma2/ scma2 * 2 ccma1/ scma1 * 2 ccma1/ scma1 * 2 ccma2/ scma2 * 2
37 mb98c81013/81123/81233/81333-10 erase cycle timing diagram (ce# = controlled, reset# = v ih ) notes: *1. see ?unction truth table? *2. ccma1/ccma2 = command address for chip erase, scma1/scma2 = command address for sector erase, sa = sector address. see ?ommand definition table? :unde?ed addresses * 1 v ih v il v ih v il v ih v il v ih v il data * 1 v ih/oh v il/ol v cc t wc t as t ah 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle aah (aaaah) 55h (5555h) 80h (8080h) t cph t ws t wh t ghel t cp t ds t vcs t dh aah (aaaah) 55h (5555h) 10h/30h (1010h/3030h) 5th bus cycle 6th bus cycle oe# we# ce# * 1 ccma1/ scma1 * 2 ccma1/ sa * 2 ccma2/ scma2 * 2 ccma1/ scma1 * 2 ccma1/ scma1 * 2 ccma2/ scma2 * 2
38 mb98c81013/81123/81233/81333-10 data# polling cycle timing diagram (reset# = v ih ) notes: *1. va = pa for programming cycle, va = sa for sector erase, va = ca for chip erase. *2. see ?unction truth table? *3. t eheh1 , 2 for ce# control. *4. program/erase operation is ?ished. :unde?ed addresses * 2 v ih v il v ih v il v ih v il v ih v il d7, d15 v ih/oh v il/ol d0-d6 * 2 d8-d14 t wc t chz command write cycle data# polling read cycle va * 1 d7, d15 d7#, d15# d7, d15 valid data d0-d6, d8-d14 d0-d6, d8-d14 invalid data d0-d6, d8-d14 valid data * 2 t acc t ce t ohz t oeh t oe * 4 v ih/oh v il/ol oe# we# ce# * 2 t whwh1,2 (t eheh1,2 ) * 3
39 mb98c81013/81123/81233/81333-10 toggle bit timing diagram (reset# = v ih ) notes: *1. va = pa for programming cycle, va = sa for sector erase, va = ca for chip erase. *2. see ?unction truth table? *3. program/erase operation is ?ished. *4. pd, 10h (1010h) or 30h (3030h) :unde?ed addresses * 2 v ih v il v ih v il v ih v il v ih v il data * 2 v ih/oh v il/ol t oeh command write cycle * 4 d6, d14 toggle d6, d14 toggle d6, d14 stop toggling valid data t oe t rc va * 1 va * 1 va * 1 va * 1 toggle bit read cycle * 3 oe# we# ce# * 2
40 mb98c81013/81123/81233/81333-10 busy# timing diagram during program/erase operations (except for mb98c81013) reset# timing diagram (except for mb98c81013) entire programming or erase operation busy# ce# we# t rsy t rp t rdy reset# possible next operation
41 mb98c81013/81123/81233/81333-10 n unique features write protect switch ?on protect write protect switch ?rotect host miniature card miniature card 1 2 3 4 1 2 3 4 1 2 1 2 2 1 2 3 2 3 2 3 5v only host 5v only miniature card 3.3v/5v host 3.3v/5v miniature card 3.3v only host 3.3v only miniature card mb98c81013/ 81123/81233/ 81333 is applied for this key voltage selection the miniature card voltage is identi?d by both a mechanical key and voltage sense signals (vs1#, vs2#). the combination of the two allow the host to determine the proper voltage required to operate the miniature card, as well as a physical means to keep cards out of host systems that may damage the cards because of improper operational voltage. six different voltage key combinations are de?ed in ?iniature card speci?ation? 5 volt only, 3.3 volt only, x.x volt only, 3v/5v, x.xv/3v, and x.xv/3v/5v. these keys consist of notches in the miniature card and corresponding tabs in the socket. the socket tabs are located in the front of the miniature card socket and are used to keep out cards that do not contain the corresponding notch. see voltage keying mechanism below. (now only de?ed about 5.0v and 3.3v)
42 mb98c81013/81123/81233/81333-10 n attribute information structure (ais) address data attribute 0000 01 [common memory device information tuple] 0001 03 link to next tuple 0002 54 flash memory with 100ns access time 0003 0d 1mb device size for common memory [mb98c81013] 1d 2mb device size for common memory [mb98c81123] 0e 4mb device size for common memory [mb98c81223] 1e 8mb device size for common memory [mb98c81333] 0004 ff end of list 05 - 0d 00 [nulltuple-ignore] 000e 80 [vendor unique tuple] 000f f1 link to next tuple 0010 99 ?iniature card identi?r 0011 10 ?evel of compliance 0012 2f ?is checksum (b00-ad1=2f) [mb98c81013] fc ?is checksum (c00-b04=fc) [mb98c81123] 91 ?is checksum (b00-a6f=91) [MB98C81233] 8d ?is checksum (b00-a73=8d) [mb98c81333] 0013 46 ?anufacture name (f) 0014 55 (u) 0015 4a (j) 0016 49 (i) 0017 54 (t) 0018 53 (s) 0019 55 (u) 001a 00 001b 4c (l) 001c 49 (i) 001d 4d (m) 001e 49 (i) 001f 54 (t) 0020 45 (e) 0021 44 (d)
43 mb98c81013/81123/81233/81333-10 n attribute information structure (ais) (continued) address data attribute 0022 00 0023 00 0024 00 0025 00 0026 00 0027 4d ?ard name (m) 0028 42 (b) 0029 39 (9) 002a 38 (8) 002b 43 (c) 002c 38 (8) 002d 30 (0) 002e 30 (0) 002f 31 (1) mb98c81013 32 (2) mb98c81123 33 (3) MB98C81233, mb98c81333 0030 33 (3) 0031 00 0032 73 (s) 0033 65 (e) 0034 72 (r) 0035 69 (i) 0036 65 (e) 0037 73 (s) 0038 00 0039 00 003a 00 003b 01 ?echnology count (1) 003c 00 ?eserved 003d 00 ?eserved 003e 00 ?eserved 003f 00 ?eserved
44 mb98c81013/81123/81233/81333-10 n attribute information structure (ais) (continued) address data attribute 0040 00 ?emory type (flash) 0041 04 ?edec manufacture id (fujitsu) 0042 a4 ?edec component id (mbm29f040a) [mb98c81013] d5 ?edec component id (mbm29f080) [mb98c81123] 3d ?edec component id (mbm29f017) [MB98C81233, mb98c81333] 0043 00 ?emory size (1mb) [mb98c81013] 01 ?emory size (2mb) [mb98c81123] 03 ?emory size (4mb) [MB98C81233] 07 ?emory size (8mb) [mb98c81333] 0044 00 ?.x v access time (not supported) 0045 00 ?.3 v access time (not supported) 0046 0a ?.0 v access time (100 ns) 0047 00 ?.x v read/write (not supported) 0048 00 ?.3 v read/write (not supported) 0049 78 ?.0 v read/write (70 ma/80 ma) 004a 01 ?tandby current (100 m a) 004b 00 ?eserved 004c 00 ?eserved 004d 00 ?eserved 004e 00 ?eserved 004f 00 ?eserved 00ff 00 ?eserved 0100 ff end of list 0101 15 [level 1 version/product-information tuple] 0102 1c link to next tuple 0103 05 pc card standard, february 1995 0104 00 0105 46 (f) 0106 55 (u) 0107 4a (j) 0108 49 (i) 0109 54 (t)
45 mb98c81013/81123/81233/81333-10 n attribute information structure (ais) (continued) address data attribute 010a 53 (s) 010b 55 (u) 010c 00 010d 4d (m) 010e 42 (b) 010f 39 (9) 0110 38 (8) 0111 43 (c) 0112 38 (8) 0113 30 (0) 0114 30 (0) 0115 31 (1) 32 (2) 33 (3) 0116 33 (3) 0117 73 (s) 0118 65 (e) 0119 72 (r) 011a 69 (i) 011b 65 (e) 011c 73 (s) 011d 00 011e ff end of list 011f 18 [jedec programming information for common memory tuple] 0120 03 link to next tuple 0121 04 jedec manufacture id (fujitsu) 0122 a4 jedec device id (mb29f040a) [mb98c81013] d5 jedec device id (mb29f080) [mb98c81123] 3d jedec device id (mb29f017) [MB98C81233, mb98c81333] 0123 ff end of list 0124 1e [device geometry information for common memory device tuple] 0125 07 link to next tuple
46 mb98c81013/81123/81233/81333-10 n attribute information structure (ais) (continued) notice: ais is programed from the address ?000h of lower byte. this ais may be deleted on the driver software which does not consider ais. address data attribute 0126 02 system bus width is 2 bytes 0127 11 erase block size is 64 kbytes 0128 01 read block size is 1 bytes 0129 01 write block size is 1 bytes 012a 01 no special partitioning requirements 012b 01 non interleaved 012c ff end of list 012d 12 [longlink to common memory] 012e 05 link to next tuple 012f 00 target address; stored as an unsigned long, low-order byte ?st 0130 00 0131 02 0132 00 0133 ff end of list 0134 ff [the end-of-chain tuple]
47 mb98c81013/81123/81233/81333-10 n package dimensions 60-pin miniature card (case no.: crd-60p-m01) c 1996 fujitsu limited k60001sc-1-1 2.50(.098)min 33.000.13(1.299.005) 38.000.13 (1.496.005) 0.77(.030) 2.50(.098)typ 15.24(.600) 3.500.13 (.138.005) 1.52(.060) "a" 8.00(.315) 5.50(.217) 5.50(.217) 8.00(.315) 18.00 1.68(.066) 18?typ 2-r0.50(.020) 4.1250.05 (.162.002) 3.810.08 (.150.003) 6.210.08 (.244.003) 33.000.13 (1.299.005) (.709) "b" 0.500.036 (.020.001) details of "b" part 1.00(.039)typ 0.85(.033) 0.50(.020) 3.25(.128)typ 4.25(.167)typ 2.70 (.106) 2.48 (.098) 4.58 (.180) 9.10 (.358) r1.00(.039) r0.15 7.62(.300) details of "a" part 1.60 2.60 (.063) (.102) 0.500.05 (.020.002) 1.25(.049) min (.006) 1.85(.073) typ 12.70(.500) 7.20(.283) 3.00 2.50 (.098) (.118) 1 pin 3.400.05 (.134.002) 5.95(.234) dimension mm (in inches)
48 mb98c81013/81123/81233/81333-10 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

▲Up To Search▲

Price & Availability of MB98C81233

	To Download MB98C81233 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .